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Microchip Technology /ATSAMV70Q19 /PMC /APLLACR

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Interpret as APLLACR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DCOFLTSEL 0FLTSEL0BIAS

Description

Audio PLL Analog Configuration Register

Fields

DCOFLTSEL

DCO Filter Selection
FLTSEL

PLL Filter Selection
BIAS

Bias Voltage Selection

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data